Overview of PHENIX MuTr ARCNet Software





Muon Tracker FEE ARCNet Architecture

A Muon Tracker Front End Module (FEM) consists of two Cathode Readout Cards(CROC) and one controller card(CNTL). The CROCs contain the CPA chips and the AMU/ADC chips. The CNTL board contains the FPGA, some chips to control the copper data link, and a place to insert the Generic ARCNet Board(GAB). The I/O ports on the GABs 8051 processor are routed to various places on the CROC and CNTL boards as shown in the control board schematic. The ARCNet connectors are labeled CON1 and CON2. If you trace the connections you will see that they interface to all the components that ARCNet must control. The CPA, AMU/ADC, and FPGA serial strings are controlled via the S_ADDR(n), SCLK, RD_WR, SD_IN, LATCH, SD_A, SD_B, and SD_C lines. These lines have the following meanings:
S_ADDR(n)Serial address select lines, used to select between CPA, AMU/ADC, or FPGA serial strings.
SCLKSerial clock, clocks in the data on SD_IN.
RD_WRControls whether you are writing to or reading from the serial string.
SD_INHolds the data you are clocking in.
LATCHLatches the serial data into the registers.
SD_ASerial data from CROC A.
SD_BSerial data from CROC B.
SD_CSerial data from FPGA.

The Dallas microLAN is controlled by the 8051's serial port. The relevant pins are RXD(serial data reciever) and TXD(serial data transmitter).

The JTAG port involves the pins EPC2_SEL, GAB_TMS, GAB_TDI, GAB_TDO, and GAB_TCLK. The usage of these pins is as follows:
EPC2_SELEnables communication with the EPC2 device.
GAB_TMSJTAG mode select signal.
GAB_TDIJTAG data to EPC2 device.
GAB_TDOJTAG data from EPC2 device.
GAB_TCLKJTAG data clock signal.

The CNTL_RST pin is connected to the FPGA external reset line.



Mapping Hardware Pins to 8051 Ports

Signals on the pins described above are controlled with the C program that configures the 8051 ROM. If you read the GAB manual (available here), you will see that the 8051 I/O ports have names in the C programming, which enables you to set the state of the port. The following table shows the 8051 ports, and how those ports map to the pins discussed above.

8051 namePin mapping
-----------------
CS0S_ADDR(0)
CS1S_ADDR(1)
CS2S_ADDR(2)
CS3S_ADDR(3)
CS4S_ADDR(4)
CS5EPC2_SEL
CS6not used
CS7not used
CS8SD_IN
CS9SCLK
CS10LATCH
CS11RD_WR
CS12not used
CS13GAB_TDI
CS14GAB_TCLK
CS15GAB_TMS
P1.0SD_A
P1.1SD_B
P1.2SD_C
P1.3GAB_TDO
P1.4-P1.7not used
PWcontrols P1 direction
PRRCNTL_RST
PRnot used
TXDTXD
RXDRXD

The chip select pins (CS0-15) are output only pins. They are divided into two bytes, the low chip select(LCS) and high chip select(HCS). You must write to these ports bytewise, you cannot access individul bits. PRR is an input/output pin, although we only use it as output. PW controls whether P1 is an input or output port. P1 can be accessed bitwise.



The 8051 C compiler

In order to turn our C program into something that the 8051 can use, we have to use an 8051 C-compiler. I am using an 8051 compiler from IAR Systems, Inc. The output format is specified as Motorola, and a C program is used to convert the Motorola format to a format that can be transmitted to the GAB.

Configuration Files

I have chosen to maintain seperate GAB configuration files for the FEMs, glink cards, and calibration card. gfem.c contains all the functions to set the serial strings, control the Dallas microLAN, and reset the FPGA. Jbi51pro.c contains the code to configure the EPC2 EEPROM through the JTAG port for .jbc files that are less than 39K in size (the maximum memory space available on the ARCNet card). Jbi51pro_39K.c contains the code to configure the EPC2 EEPROM through the JTAG port for .jbc files that are larger than 39K in size. calib.c has the functions relating to the calibration system. glink.c has the functions relating to the glink/clink cards.


The JTAG Interface

The FLEX10K50E FPGA on the controller board is configured with an EPC2 EEPROM. The EPC2 device is connected to ARCNet through a JTAG (Joint Test and Action Group) interface. The JTAG protocol is hopelessly complicated for the non expert, but you can learn the basics by looking at the appropriate documents on my reading list. In order to program the EPC2 device through the JTAG port, the 8051 must run a Jam Byte Code player. What is a Jam Byte Code player, you ask? Well, the EPC2 device is configured with a jbc file. This file contains data and also a programming algorithm. The Jam Byte Code Player must read this algorithm from the file and decide what data should go to the JTAG port. A simplistic view is that the Jam Byte Code player reads a command from the jbc file, and creates the appropriate signals on the JTAG lines. Sounds complicated? It is. Fortunately, there exists a Jam Byte Code player for embedded 8051 processors at the Jam website. It was necessary to make significant changes to the program to conform to our board architecture, to interact with ARCNet, and to deal with memory limitations on the ARCNet board. The jbc file must first be downloaded to the 8051 RAM, and then the Jam Byte Code player will program it into the EPC2 device.


The Dallas microLAN

There are two flavors of Dallas chips, the DS2480 1-wire line driver, and the DS2437 smart battery monitor chip. The DS2437 chips can measure one current, one temperature, and two voltages. We use these chips to monitor the operating state of the FEM. All communication with the DS2437 chips is done via a 1-wire interface. This means that there is a very complicated timing and signaling protocol that must be followed to avoid data collision on the wire. The DS2480 line driver relieves the programmer from having to worry about generating these signals. The DS2480 takes regular RS232 serial port signals and produces the corresponding 1-wire waveforms. Thus, the 1-wire microLAN can be controlled with the 8051 serial port.




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